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Dual 50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
Pin Description (continued)
PIN
30
31
NAME
REG_OUT
AMPSET
FUNCTION
Regulator Output. Bypass with 1 F F capacitor.
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V operation on pins
V CC_AMP_1 and V CC_AMP_2 . Set to logic 0 for 5V operation.
32
AMP_OUT_1 Driver Amplifier Output (50 I ), Path 1. Connect a pullup inductor from AMP_OUT_1 to V CC_.
34
35
37
38
39
40
41
—
PD_1
AMP_IN_1
V CC_AMP_1
A_ATT_OUT_1
A_VCTL_1
AA_SP
A_ATT_IN_1
EP
Power-Down, Path 1. See Table 2 for operation details.
Driver Amplifier Input (50 I ), Path 1. Requires a DC-blocking capacitor. Connect to
A_ATT_OUT_1 through a 1000pF capacitor.
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
Analog Attenuator Output (50 I ), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
Analog Attenuator Voltage-Control Input, Path 1. Bypass to ground with a 150pF capacitor
if on-chip DAC is used (AA_SP = 1).
DAC Enable/Disable Logic Input for Analog Attenuators. Set AA_SP to logic 1 to enable on-chip
DAC circuit and digital SPI control. Set AA_SP to logic 0 to disable DAC circuit and digital SPI
control. When AA_SP = 0, use analog control lines (A_VCTL_1 and A_VCTL_2).
Analog Attenuator Input (50 I ), Path 1. Requires a 1000pF DC-blocking capacitor.
Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper RF
performance and enhanced thermal dissipation.
Detailed Description
The MAX2064 high-linearity analog VGA is a gener-
al-purpose, high-performance amplifier designed to
interface with 50 I systems operating in the 50MHz to
1000MHz frequency range.
Each channel of the device integrates an analog attenua-
tor to provide 33dB of total gain control, as well as a driver
amplifier optimized to provide high gain, high IP3, low NF,
and low power consumption.
Each analog attenuator is controlled using an external
voltage or through the SPI-compatible interface using
an on-chip 8-bit DAC. See the Applications Information
section and Table 3 for attenuator programming details.
Because each of the two stages in the separate signal
paths has its own RF input and RF output, this compo-
nent can be configured to either optimize NF (amplifier
configured first) or OIP3 (amplifier last). The device’s per-
formance features include 24dB amplifier gain (amplifier
only), 4.4dB NF at maximum gain (includes attenuator
insertion losses), and a high OIP3 level of +41dBm. Each
of these features makes the device an ideal VGA for mul-
tipath receiver and transmitter applications.
In addition, the device operates from a single +5V
supply with full performance, or a +3.3V supply for an
enhanced power-savings mode with lower performance.
The device is available in a compact 48-pin TQFN pack-
age (7mm x 7mm) with an exposed pad. Electrical per-
formance is guaranteed over the extended temperature
range, from T C = -40 N C to +85 N C.
Analog Attenuator Control
The device integrates two analog attenuators. Each
analog attenuator has a 33dB range and is controlled
using an external voltage, or through the 3-wire SPI inter-
face using an on-chip 8-bit DAC. See the Applications
Information section and Table 3 for attenuator program-
ming details. The attenuators can be used for both static
and dynamic power control.
Note that when the analog attenuators are controlled by the
DACs through the SPI bus, the DAC output voltage shows
on A_VCTL_1 and A_VCTL_2 (pins 39 and 22, respective-
ly). Therefore, in SPI mode, the A_VCTL_1 and A_VCTL_2
pins must only connect to the resistor and capacitor to
ground, as shown in the Typical Application Circuit .
14
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